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asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 1 - g eneral d escription the ak4355 offers the perfect mix for cost and performance based multi - channel audio systems. akm's advanced multi - bit architecture delivers a wide dynamic range and low outband noise. the ak4355 has fu ll differential scf outputs, removing the need for ac coupling capacitors and increasing performance for systems with excessive clock jitter. the 24 bit word length and 192khz sampling rate make this part ideal for a wide range of application including dvd - audio. f eatures o sampling rate: 8khz to 192khz o 24bit 8 times digital filter with slow roll - off option o thd+n: - 90db o dr, s/n: 106db o high tolerance to clock jitter o low distortion differential output o digital de - emphasis for 32, 44.1 & 48khz sampling o zero detect pin o channel independent digital attenuator with soft - transition o soft mute o i/f format: 24 - bit msb justified, 24/20/16 - bit lsb justified or i 2 s o master clock normal speed: 256fs, 384fs, 512fs or 768fs double speed: 12 8fs, 192fs, 256fs or 384fs quad speed : 128fs , 192fs o power supply: 4.75 to 5.25v o 28pin vsop package scf dac datt dzf lout1+ lout1- scf dac datt rout1+ rout1- scf dac datt lout2+ lout2- scf dac datt rout2+ rout2- scf dac datt lout3+ lout3- scf dac datt rout3+ rout3- audio i/f control register ak4355 mclk lrck bick sdti1 sdti2 sdti3 csn cclk cdti 192khz 24 - bit 6ch dac for dvd - audio ak4 355
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 2 - n ordering guide AK4355VF - 40 ~ +85 c 28pin vsop (0.65mm pitch) akd4355 evaluation board for ak 4355 n pin layout 6 5 4 3 2 1 vref dzf mclk pdn bick sdti1 7 sdti3 8 avdd avss lout1+ lout1- rout1+ rout1- lout2+ lout2- top view 10 9 lrck csn cclk 11 cdti 12 rout2+ rout2- lout3+ lout3- 23 24 25 26 27 28 22 21 19 20 18 17 sdti2 dvdd 1 3 dvss 1 4 rout3+ rout3- 16 15
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 3 - p in /f unction no. pin name i/o function 1 vref i positive voltage reference input pin 2 dzf o zero input detect pin 3 pdn i power - down mode pin when at ? l ? , the ak4355 is in the power - down mode an d is held in reset. the ak4355 should always be reset upon power - up. 4 mclk i master clock input pin an external ttl clock should be input on this pin. 5 bick i audio serial data clock pin 6 sdti1 i dac1 audio serial data input pin 7 sdti2 i dac2 audio serial data input pin 8 sdti3 i dac3 audio serial data input pin 9 lrck i l/r clock pin 10 csn i chip select pin 11 cclk i control clock pin 12 cdti i control data input pin 13 dvdd - digital power supply pin 14 dvss - digital ground pin 1 5 rout3 - o dac3 rch negative analog output pin 16 rout3+ o dac3 rch positive analog output pin 17 lout3 - o dac3 lch negative analog output pin 18 lout3+ o dac3 lch positive analog output pin 19 rout2 - o dac2 rch negative analog output pin 20 rout2+ o dac2 rch positive analog output pin 21 lout2 - o dac2 lch negative analog output pin 22 lout2+ o dac2 lch positive analog output pin 23 rout1 - o dac1 rch negative analog output pin 24 rout1+ o dac1 rch positive analog output pin 25 lout1 - o dac1 lch ne gative analog output pin 26 lout1+ o dac1 lch positive analog output pin 27 avss - analog ground pin 28 avdd - analog power supply pin note: all input pins should not be left floating.
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 4 - a bsolute maximum ratings (avss, dvss =0v ; note 1) parameter symbol min max units power supplies analog digital |avss - dvss| (note 2) a vdd d vd d d gnd - 0.3 - 0.3 - 6.0 6.0 0.3 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina - 0.3 a vdd +0.3 v digital input voltage vind - 0.3 d v d d+0.3 v ambient operating temperature ta - 4 0 85 c storage temperature tstg - 65 150 c note : 1 . all voltages with respect to ground . 2. avss and dvss must be connected to the same analog ground plane . warning : operation at or beyond these limits ma y results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss =0v ; note 1) parameter symbol min typ max units power supplies (note 3) analog d igital a v dd d vdd 4.75 4.75 5.0 5.0 5.25 5.25 v v voltage reference vref avdd - 0.5 - avdd v note: 1. all voltages with respect to ground. 3. the power up sequence between avdd and dvdd is not critical. *akm assumes no responsibility for the usage beyond the conditio ns in this datasheet.
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 5 - analog characteristics ( ta=25 c ; avdd , dvdd = 5 v ; vref=avdd ; fs=4 4.1k hz ; bick=64fs; signal frequency=1khz ; 24bit input data; measurement frequency=20hz ~ 20khz; r l 3 4k w ; unless otherwise specified ) parameter min typ max units re solution 24 bits dynamic characteristics (note 4) fs=44.1khz bw=20khz 0dbfs - 60dbfs - 90 - 42 - 86 - db db fs=96khz bw=40khz 0dbfs - 60dbfs - 88 - 39 - 84 - db db thd+n fs=192khz bw=40khz 0dbfs - 60dbfs - 86 - 39 - - db db dynamic range ( - 60dbfs with a - weighted) (note 5) 100 106 db s/n (a - weighted) (note 6) 100 106 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c output voltage (note 7) 3.0 3.2 3.4 vpp load resistance (note 8) 4 k w power supplies power su pply current (avdd+dvdd) normal operation (pdn = ? h ? , fs 96khz ) normal operation (pdn = ? h ? , fs=192khz ) power - down mode (pdn = ? l ? ) (note 9) 49 55 10 75 80 100 ma ma a notes: 4. measured by audio precision (system two) or upd. r efer to the evaluation board manual. 5. 100db at 16bit data. 6. s/n does not depend on input bit length. 7. full - scale voltage (0db). output voltage scales with the voltage of vref, aout (typ.@0db)=(aout+) - (aout - )= 3.2vpp vref/5. 8. for ac - load. 4 k w for dc - load. 9. all digital inputs including clock pins (mclk, bick and lrck) are held dvdd or dvss.
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 6 - sharp roll - off filter characteristics ( ta = 25 c ; avdd, dvdd = 4.75 ~ 5.25 v ; fs = 4 4.1k hz ; dem = off; slow= ? 0 ? ) parameter symbol min typ max units digit al filter passband 0.05db (note 10) - 6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 10) sb 24.25 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group d elay (note 11) gd - 20.5 - 1/fs digital filter + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.2 0.3 +0/ - 0.6 - - - db db db note s: 10. the passband and stopband frequencies scale with fs ( system sampling rate). for example, pb=0.4535 fs (@ 0.05db), sb=0.546 fs. 11. the calculating delay time which occurred by digital filtering. this time is from setting the 16/24bit data of both channels to input register to the outpu t of analog signal. slow roll - off f ilter characteristics (ta = 25 c ; avdd, dvdd = 4.75~5.25v; fs = 44.1 khz; dem = off; slow = ? 1 ?) parameter symbol min typ max units digital filter passband 0.04db (note 12) - 3.0db pb 0 - 18.2 8.1 - khz khz stopband (note 12) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 11) gd - 20.5 - 1/fs di gital filter + scf frequency response 20.0khz 40.0khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0/ - 5 +0/ - 4 +0/ - 5 - - - db db db note: 12 . the passband and stopband frequencies scale with fs. for example, pb = 0. 185 fs (@ 0.0 4 db ), sb = 0. 888 fs. dc characteristics ( ta= 25 c ; avdd, dvdd = 4.75 ~ 5.25 v ) parameter symbol min typ max units high - level input voltage low - level input voltage vih vil 2.2 - - - - 0.8 v v high - level output voltage (iout= - 80 a) low - level output volt age (iout=80 a) voh vol dvdd - 0.4 - - - 0.4 v v input leakage current iin - - 10 a
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 7 - switching characteristics ( ta= 25 c ; avdd, dvdd = 4.75 ~ 5.25 v ; c l =20pf) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal speed mode double speed mode qu ad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % audio interface timing bick period normal speed mode double/quad speed mode bick pulse width low pulse width high bick rising to lrck edge (note 13) lrck edge to bick rising (note 13) sdti hold time sdti setup time tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ? h ? time csn ? ? to cclk ? - ? c clk ? - ? to csn ? - ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns reset timing pdn pulse width (note 14) tpd 150 ns no t e s: 13. bick rising edge must not occur at the same time as lrck edge. 14. the ak4355 can be reset by bringing pdn = ? l ? .
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 8 - n timing diagram 1/fclk tclkl vih tclkh mclk vil dclk =tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr serial interface timing
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 9 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing tpd vil pdn power - down timing
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 10 - operation overview n system clock the external clo cks, which are required to operate the ak43 55 , are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. ther e are two methods to set mclk frequency. in manual setting mode (acks = ? 0 ? : register 00h), the sampling speed is set by dfs0/1(table 1). t he frequency of mclk at each sampling speed is set automatically. (table 2 ~ 4 ). in auto setting mode (acks = ? 1 ? : def ault), as mclk frequency is detected automatically (table 5), and the internal master clock becomes the appropriate frequency (table 6), it is not necessary to set dfs0/1. all external clocks (mclk,bick and lrck) should always be present whenever the ak43 55 is in the normal operation mode ( pdn= ? h ? ). if these clocks are not provided, the ak4355 may draw excess current may fall into unpredictable operation. this is because the device utilizes dynamic refreshed logic internally. the ak4355 should be reset by pdn= ? l ? after threse clocks are provided. if the external clocks are not present, the ak4355 should be in the power - down mode (pdn= ? l ? ). after exiting reset at power - up etc., the ak4355 is in the power - down mode until mclk and lrck are input. dfs1 dfs 0 sampling rate (fs) 0 0 normal speed mode 8khz ~ 48khz default 0 1 double speed mode 60khz ~ 96khz 1 0 quad speed mode 120khz ~ 192khz table 1. sampling speed (manual setting mode) lrck mclk bick fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920mhz 12. 2880mhz 16.3840mhz 24.5760mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 3.0720mhz table 2. system clock example (normal speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 3. system clock example (double speed mode @manual setting mode) lrck mclk bick fs 128 fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 11.2896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz table 4. system clock example (quad speed mode @manual setting mode)
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 11 - mclk sampling speed 512fs 768fs normal 256fs 384fs double 128fs 192fs quad ta ble 5. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.8640 - - - - quad table 6. system clock example (auto setting mode) n audio serial interface format data is shifted in via these sdti1, sdti2, and sdti3 pins using bick and lrck inputs. the dif0 - 2 as shown in table 7 can select five serial data modes . in all modes the serial data is msb - first, 2 ? s compliment format and is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified format s by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti format bick figure 0 0 0 0 16bit lsb justified 3 32fs figure 1 1 0 0 1 20bit lsb justified 3 40fs figure 2 2 0 1 0 24bit msb justified 3 48fs figure 3 default 3 0 1 1 24bit i 2 s compatible 3 48fs figur e 4 4 1 0 0 24bit lsb justified 3 48fs figure 2 table 7. audio data formats sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 (32fs) (64fs) 0 14 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don ? t care don ? t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 12 - sdti lrck bick (64fs) 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don ? t care don ? t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don ? t care don ? t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing lrck bick (64fs) sdti 0 22 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don ? t care 23 lch data rch data 23 30 22 2 24 23 30 22 1 0 don ? t care 23 22 23 figure 3. mode 2 timing lrck bick (64fs) sdti 0 3 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don ? t care 23 lch data rch data 23 25 3 2 24 23 25 22 1 0 don ? t care 23 23 figure 4. mode 3 timing
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 13 - n de - emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem0 and dem1. in case of double speed and quad speed mode, the digital de-emphasis filter is always off. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 8 . de-emphasis f ilter c ontrol ( normal speed mode) n output volume the ak43 55 includes channel independent digital output volumes (att) with 256 levels including mute and 0.5db step . these volumes are in front of the dac and can attenuate the input data from 0db to ? 127 db and mute. transition time is set by ast1 - 0 bits(table10).in mode0 and mode1, w hen changing levels, transitions are exe cuted via soft changes; thus no switching noise occurs during these transitions. att7 - 0 attenuation level ffh 0db feh - 0.5db fdh - 1.0db : : 02h - 126.5db 01h - 127.0db 00h mute ( - ) default table 9. attenuation level of outp ut volume mode ats1 ats0 att speed 0 0 0 7424/fs 1 0 1 1061/fs 2 1 0 256/fs 3 1 1 reserved default table 10. transition time of output volume in case of mode0, it takes 7424/ fs( 168ms@fs=44.1k) to transit from ffh(0db) to 00 h( mute). in case of mode1, it takes 1061/ fs( 24ms@fs=44.1k) to transit from ffh(0db) to 00 h( mute). in case mode2 and 3,it takes 256/ fs( 6ms@fs=44.1k) to transit from ffh(0db) to 00 h ( mute). if pdn pin goes to ? l ?, att 7 - 0 registers are initialized to ffh.attn7 - 0 registers go to ffh when rstn bit is set to ? 0 ? . when rstn bit returns to ? 1 ? , att7 - 0 registers go to the set value. digital output volume function is independent of soft mute function.
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 14 - n zero d etection when the input data at all channel is continuously zero s for 81 92 lrck cycles, dzf pin goes to ? h ?. dzf pin immediately goes to ? l ? if input data of each channel is not zero after going dzf ? h ?. if rstn bit is ? 0 ?, dzf pin go es to ? h ?. dzf pin go es to ? l ? at 4 ~ 5lrck if input data of each channel is not zero after rstn bit returns to ? 1 ?. zero detect function can be disabled by dzfe bit. in this case, dzf pins of both channels are always ? l ?. dzfb bit can invert the polarity of dzf pin. when one of pw1 - 3 bit is set to ? 0 ? , the input data of dac which the pw bit is set t o ? 0 ? should be zero in order to enable zero detection of the other channels . when all pw1 - 3 bits are set to ? 0 ? , dzf pin fixes ? l ? . n soft mute operation soft mute operation is performed at digital domain. when the smute bit goes to ? 1 ? , the output sig nal is attenuated by - during 1024 lrck cycles. when the smute bit is returned to ? 1 ? , the mute is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute pin attenuation dzf pin 1024/fs 0db - aout 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) the output signal is attenuated by - during 10 24 lrck cycles (1024/fs). (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db. (4) when the input data at each cha nnel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ? h ? . dzf pin immediately goes to ? l ? if input data are not zero after going dzf ? h ? . figure 5. soft mute and zero detection
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 15 - n system reset the ak4355 should be reset once by bringing pdn = ? l ? upon power - up. the ak4355 is powered up and the internal timing starts clocking by lrck ? - ? after exiting reset and power down state by mclk. the ak4355 is in the power - down mode until mclk and lrck are input. n power - down the ak4355 is placed in the power - down mode by bringing pdn pin ? l ? and the anlog outputs are floating (hi - z). figure 6 shows an example of the system timing at the power - down and power - up. each dac can be powered down by each power - down bit (pw1 - 3) ? 0 ? . in t his case, the internal register values are not initialized and the analog output is hi - z. because some click noise occurs, the analog output should be muted externally if the click noise influences system application. normal operation internal state pdn power-down n ormal operation gd gd ? 0 ? data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzfl/dzfr external mute (5) (3) (1) mute on (2) (4) don ? t care notes: ( 1) the a nalog output corresponding to digital input ha s the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal . this noise is output even if ? 0 ? data is input. (4) t he ext ernal clocks (mclk, bick and lrck) can be stopped in the power-down mode (pdn = ? l ? ) . (5) please mute the analog output externally if the click noise ( 3 ) influences system application. the timing example is shown in this figure. (6) dzf pins are ? l ? in th e power - down mode (pdn = ? l ? ). figure 6. power-down/up se quence e xample
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 16 - n reset function when rstn =0, dac is powered down but the internal register values are not initialized. the analog outputs go to avdd/2 voltage and dzf pin go es to "h". figure 7 sho ws the example of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd ? 0 ? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzf (3) (1) (2) normal operation 2/ fs( 5) internal rstn bit 2~3/fs (6) 3~4/fs (6) don ? t care (4) notes: ( 1) the a nalog output corresponding to digital input ha s the group delay (gd). (2) analog outputs go to avdd/2 . (3) click noise occurs at the edges( ? - ? ) of the internal timing of rstn bit . this noise is output even if ? 0 ? data is input. (4) t he external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = ? l ? ) . (5) dzf pins go to ? h ? when the rstn bit becomes ? 0 ?, and go to ? l ? at 2/fs after rstn bit becomes ? 1 ?. (6) there is a delay, 3 ~ 4/fs from rstn bit ?0? to the internal rstn bit ? 0 ? , and 2 ~ 3/fs from rstn bit ? 1 ? to the internal rstn ? 1 ? . figure 7. reset sequence example
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 17 - n mode control interface internal registers may be written by 3 - wire p interface pins , csn , cclk and cdti. the data on this interface consists of c hip a ddress (2bits, c 1/0 ; fixed to ? 1 1?), read/write (1bit; fixed to ?1? , write only ), register a ddress (msb first, 5bits) and control d ata (msb first, 8bits). the ak43 55 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by csn ? - ?. the clock speed of cclk is 5mhz (max). pdn = ?l? resets the registers to their default values. t he internal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk csn c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1 - c0: chip address (fixed to ? 11 ? ) r/w: read/write (fixed to ? 1 ? , write only) a4 - a0: register address d7 - d0: control data figure 8 . control i/f timing * ak43 55 does not support the read command and chip address. c 1/0 and r/w are fixed to ? 1 11? *when the ak4355 is in the power down mode (pdn = ? l ? ) or the mclk is not provided, writing into the control register is inhibited . n register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks slow 0 dzfe dif2 dif1 dif0 rstn 01h control 2 0 0 0 0 0 0 smut e rstn 02h speed & power down control 0 0 dfs1 dfs0 pw3 pw2 pw1 rstn 03h de - emphasis control 0 0 0 0 0 0 dem1 dem0 04h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h rout1 att control att7 att6 att5 att4 att3 att2 att1 att0 06h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 08h lout3 att control att7 att6 att5 att4 att3 att2 att 1 att0 09h rout3 att control att7 att6 att5 att4 att3 att2 att1 att0 0ah control 3 0 0 0 0 0 dzfb ats1 ats0 notes: for addresses from 0bh to 1fh, data must not be written. when pdn pin goes ? l ? , the registers are initialized to their default values. when rstn bit goes to ? 0 ? , the internal timing is reset, dzf pin go to ? h ? but registers are not initialized to their default values.
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 18 - n register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks slow 0 dzfe dif2 dif1 dif0 rstn d efault 1 0 0 1 0 1 0 1 rstn : internal timing reset 0: reset. dzf pin goes to ? h ? and registers are not initialized. 1: normal operation when mclk frequency or dfs change s , the ak43 55 should be reset by pdn pin or rstn bit. dif2 - 0: audio data inte rface modes (see table 7) initial: ? 010 ? , mode 2 dzfe: data zero detect enable 0: disable 1: enable zero detect function can be disabled by dzfe bit. slow: slow roll - off response enable 0: disable 1: enable acks : master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ? 1 ?. in this case, the setting of dfs1 - 0 are ignored. when this bit is ? 0 ? , dfs1 - 0 set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 0 0 0 0 smut e rstn default 0 0 0 0 0 0 0 1 rstn : internal timing reset 0: reset. dzf pin goes to ? h ? and registers are not initialized. 1: nor mal operation when mclk frequency or dfs change s , the ak43 55 should be reset by pdn pin or rstn bit. smute: soft mute enable 0: normal operation 1: all dac outputs soft - muted
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 19 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h speed & power d own control 0 0 dfs1 dfs0 pw3 pw2 pw1 rstn default 0 0 0 0 1 1 1 1 rstn : internal timing reset 0: reset. dzf pin goes to ? h ? and registers are not initialized. 1: normal operation when mclk frequency or dfs change s , the ak43 55 should be reset b y pdn pin or rstn bit. pw3 - 1: power - down control (0: power - down, 1: power - up) pw1: power down control of dac1 pw2: power down control of dac2 pw3: power down control of dac3 all sections are powered - down by pw1=pw2=pw3=0. dfs1 - 0: sampling speed control (see table 1) 00: normal speed 01: double speed 10: 4 times speed addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h de - emphasis control 0 0 0 0 0 0 dem1 dem0 default 0 0 0 0 0 0 0 1 dem1 - 0: de - empha sis response control for dac1/2/3 data on sdti1/2/3/ (see table 8) initial: ? 01 ?, off addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h rout1 att control att7 att6 att5 att4 att3 att2 att 1 att0 06h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 08h lout3 att control att7 att6 att5 att4 att3 att2 att1 att0 09h rout3 att control att7 att6 att5 att4 att3 att2 att1 at t0 default 1 1 1 1 1 1 1 1 att7 - 0: attenuation level 256 levels, 0.5db step (see table 9) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah control 3 0 0 0 0 0 dzfb ats1 ats0 default 0 0 0 0 0 0 0 0 ats1 - 0: datt speed setting (see table 10) initial: ? 00 ? , mode 0 dzfb : inverting enable of dzf 0: dzf goes ? h ? at zero detection 1: dzf goes ? l ? at zero detection
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 20 - system design figure 9 shows the system connection diagram. an evaluation board (akd4355) is available in order to allow an easy study on the layout of a surrounding circuit. vref 1 dzf 2 pdn 3 mclk 4 bick 5 sdti1 6 sdti2 7 sdti3 8 lrck 9 csn 10 cclk 11 cdti 12 avdd 28 avss 27 lout1+ 26 lout1 - 25 rout1+ 24 rout1 - 23 lout2+ 22 lout2 - 21 rout2+ 20 rout2 - 19 l out3+ 18 lout3 - 17 micro - controller 0.1u 10u + ak4355 analog 5v 13 14 16 15 dvdd dvss rout3+ rout3 - lpf lpf r1ch mut out l1ch out analog ground digital ground 0.1u lpf lpf lpf lpf mute mute mute mute mute mute l2ch r2ch l3ch r3ch out out out out master clock fs 24bit audio data 64fs reset 24bit audio data 24bit audio data + 0.1u 10u digital 5v figure 9. typical connection diagram notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resistor should be added in series between ao ut and capacitive load. - all input pins should not be left floating.
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 21 - analog ground digital ground system controller vref 1 dzf 2 pdn 3 mclk 4 bick 5 sdti1 6 sdti2 7 sdti3 8 lrck 9 csn 10 cclk 11 cdti 12 avdd 28 avss 27 lout1+ 26 lout1- 25 rout1+ 24 rout1- 23 lout2+ 22 lout2- 21 rout2+ 20 rout2- 19 lout3+ 18 lout3- ak4355 17 13 14 16 15 dvdd dvss rout3+ rout3- figure10. ground layout note: avss and dvss must be connected to the same analog ground plane. 1. grounding and power supply decoupling the ak4355 requ ires careful attention to power supply and grounding arrangements. avdd and dvdd are usually supplied from analog supply in system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the ak4355 m ust be connected to analog ground plane . system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be near to the ak4355 as possible, with the sm all value ceramic capacitors being the nearest. 2. voltage reference inputs vref sets the analog output range. vref pin is normally connected to avdd with a 0.1 m f ceramic capacitor. all signals, especially clocks, should be kept away from the vref pin in order to avoid unwanted coupling into the ak4355 3. analog outputs the analog outputs are full - differential outputs and 0.64 x vrefh vpp (typ) centered around the internal common voltage (about avdd/2). the differential outputs are summed externally, v a out =(aout+) - (aout - ) between aout+ and aout - . if the summing gain is 1, the output range is 6.4vpp (typ @vrefh=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2 ? s complement. the output voltage (v aout ) is a positive full scale for 7fffff (@24bit) and a negative full scale for 800000h (@24bit). the ideal v aout is 0v for 000000h (@24bit). the internal switched - capacitor filter and external low pass filter attenuate the noise generated by the delta - sigma modulator beyond the audio passband. dc offset on aout+/ - is eliminated without ac coupling since the analog outputs are differential. figure 11and 12 show the example of external op - amp circuit summing the differential outputs.
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 22 - 4.7k 4.7k r1 4.7k r1 4.7k 470p vop 470p vop 1k 1k 47u 0.1u bias aout- aout+ 3300p when r1=200 w when r1=180 w fc=93.2khz, q=0.712, g=-0.1db at 40khz fc=98.2khz, q=0.681, g=-0.2db at 40khz analog out figure 11 external 2 nd order lpf circuit example (using op - amp with single power supply) 4.7k 4.7k r1 4.7k r1 4.7k 470p + vop 470p - vop aout- aout+ 3300p when r1=200 w when r1=180 w fc=93.2khz, q=0.712, g=-0.1db at 40khz fc=98.2khz, q=0.681, g=-0.2db at 40khz analog out figure 12 external 2 nd order lpf circuit example (using op - amp with dual power supplies)
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 23 - package 0.1 0.1 0 -10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.1 5- 0. 0 5 0. 22 0.1 0.65 *9.8 0.2 1.25 0.2 a 1 14 15 28 28 pin vsop (unit: mm) *5.6 0.2 7.6 0.2 0.5 0.2 +0.1 0.675 n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ ak43 55 ] ms0063 - e - 01 2002/07 - 24 - marking akm ak4355 v f xxxbyyyyc xxxxbyyyyc dat e code identifier xxxb: lot num ber (x : digit number, b : alpha character ) yyyyc: assembly date (y : digit number , c : alpha character) i m portant notice these products and their specifications are subject to change without notice. before considering any use or applicati on, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of a ny information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, curre ncy exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, excep t with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the bu yer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibil ity and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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